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   <div id="projectname">CMSIS-Core (Cortex-M)
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   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<p>Structure type to access the Nested Vectored Interrupt Controller (NVIC).  
 <a href="structNVIC__Type.html#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a9fccef5a60a0d5e81fcd7869a6274f47"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a9fccef5a60a0d5e81fcd7869a6274f47">ISER</a> [8]</td></tr>
<tr class="memdesc:a9fccef5a60a0d5e81fcd7869a6274f47"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/W) Interrupt Set Enable Register.  <a href="#a9fccef5a60a0d5e81fcd7869a6274f47">More...</a><br/></td></tr>
<tr class="separator:a9fccef5a60a0d5e81fcd7869a6274f47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2de17698945ea49abd58a2d45bdc9c80"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a2de17698945ea49abd58a2d45bdc9c80">RESERVED0</a> [24]</td></tr>
<tr class="memdesc:a2de17698945ea49abd58a2d45bdc9c80"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a2de17698945ea49abd58a2d45bdc9c80">More...</a><br/></td></tr>
<tr class="separator:a2de17698945ea49abd58a2d45bdc9c80"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a245df8bac1da05c39eadabede9323203"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a245df8bac1da05c39eadabede9323203">ICER</a> [8]</td></tr>
<tr class="memdesc:a245df8bac1da05c39eadabede9323203"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x080 (R/W) Interrupt Clear Enable Register.  <a href="#a245df8bac1da05c39eadabede9323203">More...</a><br/></td></tr>
<tr class="separator:a245df8bac1da05c39eadabede9323203"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6d1daf7ab6f2ba83f57ff67ae6f571fe"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe">RSERVED1</a> [24]</td></tr>
<tr class="memdesc:a6d1daf7ab6f2ba83f57ff67ae6f571fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a6d1daf7ab6f2ba83f57ff67ae6f571fe">More...</a><br/></td></tr>
<tr class="separator:a6d1daf7ab6f2ba83f57ff67ae6f571fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8f731a9f428efc86e8d311b52ce823d0"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a8f731a9f428efc86e8d311b52ce823d0">ISPR</a> [8]</td></tr>
<tr class="memdesc:a8f731a9f428efc86e8d311b52ce823d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x100 (R/W) Interrupt Set Pending Register.  <a href="#a8f731a9f428efc86e8d311b52ce823d0">More...</a><br/></td></tr>
<tr class="separator:a8f731a9f428efc86e8d311b52ce823d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0953af43af8ec7fd5869a1d826ce5b72"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a0953af43af8ec7fd5869a1d826ce5b72">RESERVED2</a> [24]</td></tr>
<tr class="memdesc:a0953af43af8ec7fd5869a1d826ce5b72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a0953af43af8ec7fd5869a1d826ce5b72">More...</a><br/></td></tr>
<tr class="separator:a0953af43af8ec7fd5869a1d826ce5b72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8d8f45d9c5c67bba3c153c55574bac95"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a8d8f45d9c5c67bba3c153c55574bac95">ICPR</a> [8]</td></tr>
<tr class="memdesc:a8d8f45d9c5c67bba3c153c55574bac95"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x180 (R/W) Interrupt Clear Pending Register.  <a href="#a8d8f45d9c5c67bba3c153c55574bac95">More...</a><br/></td></tr>
<tr class="separator:a8d8f45d9c5c67bba3c153c55574bac95"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9dd330835dbf21471e7b5be8692d77ab"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a9dd330835dbf21471e7b5be8692d77ab">RESERVED3</a> [24]</td></tr>
<tr class="memdesc:a9dd330835dbf21471e7b5be8692d77ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a9dd330835dbf21471e7b5be8692d77ab">More...</a><br/></td></tr>
<tr class="separator:a9dd330835dbf21471e7b5be8692d77ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4bca5452748ba84d64536fb6a5d795af"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a4bca5452748ba84d64536fb6a5d795af">IABR</a> [8]</td></tr>
<tr class="memdesc:a4bca5452748ba84d64536fb6a5d795af"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x200 (R/W) Interrupt Active bit Register.  <a href="#a4bca5452748ba84d64536fb6a5d795af">More...</a><br/></td></tr>
<tr class="separator:a4bca5452748ba84d64536fb6a5d795af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5c0e5d507ac3c1bd5cdaaf9bbd177790"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790">RESERVED4</a> [56]</td></tr>
<tr class="memdesc:a5c0e5d507ac3c1bd5cdaaf9bbd177790"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a5c0e5d507ac3c1bd5cdaaf9bbd177790">More...</a><br/></td></tr>
<tr class="separator:a5c0e5d507ac3c1bd5cdaaf9bbd177790"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7ff7364a4260df67a2784811e8da4efd"><td class="memItemLeft" align="right" valign="top">__IOM uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a7ff7364a4260df67a2784811e8da4efd">IP</a> [240]</td></tr>
<tr class="memdesc:a7ff7364a4260df67a2784811e8da4efd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)  <a href="#a7ff7364a4260df67a2784811e8da4efd">More...</a><br/></td></tr>
<tr class="separator:a7ff7364a4260df67a2784811e8da4efd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4f753b4f824270175af045ac99bc12e8"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a4f753b4f824270175af045ac99bc12e8">RESERVED5</a> [644]</td></tr>
<tr class="memdesc:a4f753b4f824270175af045ac99bc12e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a4f753b4f824270175af045ac99bc12e8">More...</a><br/></td></tr>
<tr class="separator:a4f753b4f824270175af045ac99bc12e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a37de89637466e007171c6b135299bc75"><td class="memItemLeft" align="right" valign="top">__OM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a37de89637466e007171c6b135299bc75">STIR</a></td></tr>
<tr class="memdesc:a37de89637466e007171c6b135299bc75"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xE00 ( /W) Software Trigger Interrupt Register.  <a href="#a37de89637466e007171c6b135299bc75">More...</a><br/></td></tr>
<tr class="separator:a37de89637466e007171c6b135299bc75"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>Structure type to access the Nested Vectored Interrupt Controller (NVIC). </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="a4bca5452748ba84d64536fb6a5d795af"></a>
<div class="memitem">
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          <td class="memname">__IOM uint32_t NVIC_Type::IABR[8]</td>
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<p>Offset: 0x200 (R/W) Interrupt Active bit Register. </p>

</div>
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<a class="anchor" id="a245df8bac1da05c39eadabede9323203"></a>
<div class="memitem">
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          <td class="memname">__IOM uint32_t NVIC_Type::ICER[8]</td>
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<p>Offset: 0x080 (R/W) Interrupt Clear Enable Register. </p>

</div>
</div>
<a class="anchor" id="a8d8f45d9c5c67bba3c153c55574bac95"></a>
<div class="memitem">
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          <td class="memname">__IOM uint32_t NVIC_Type::ICPR[8]</td>
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</div><div class="memdoc">

<p>Offset: 0x180 (R/W) Interrupt Clear Pending Register. </p>

</div>
</div>
<a class="anchor" id="a7ff7364a4260df67a2784811e8da4efd"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">__IOM uint8_t NVIC_Type::IP[240]</td>
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</div><div class="memdoc">

<p>Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) </p>

</div>
</div>
<a class="anchor" id="a9fccef5a60a0d5e81fcd7869a6274f47"></a>
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          <td class="memname">__IOM uint32_t NVIC_Type::ISER[8]</td>
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</div><div class="memdoc">

<p>Offset: 0x000 (R/W) Interrupt Set Enable Register. </p>

</div>
</div>
<a class="anchor" id="a8f731a9f428efc86e8d311b52ce823d0"></a>
<div class="memitem">
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          <td class="memname">__IOM uint32_t NVIC_Type::ISPR[8]</td>
        </tr>
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</div><div class="memdoc">

<p>Offset: 0x100 (R/W) Interrupt Set Pending Register. </p>

</div>
</div>
<a class="anchor" id="a2de17698945ea49abd58a2d45bdc9c80"></a>
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          <td class="memname">uint32_t NVIC_Type::RESERVED0[24]</td>
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<p>Reserved. </p>

</div>
</div>
<a class="anchor" id="a0953af43af8ec7fd5869a1d826ce5b72"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">uint32_t NVIC_Type::RESERVED2[24]</td>
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</div><div class="memdoc">

<p>Reserved. </p>

</div>
</div>
<a class="anchor" id="a9dd330835dbf21471e7b5be8692d77ab"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">uint32_t NVIC_Type::RESERVED3[24]</td>
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<p>Reserved. </p>

</div>
</div>
<a class="anchor" id="a5c0e5d507ac3c1bd5cdaaf9bbd177790"></a>
<div class="memitem">
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          <td class="memname">uint32_t NVIC_Type::RESERVED4[56]</td>
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<p>Reserved. </p>

</div>
</div>
<a class="anchor" id="a4f753b4f824270175af045ac99bc12e8"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">uint32_t NVIC_Type::RESERVED5[644]</td>
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</div><div class="memdoc">

<p>Reserved. </p>

</div>
</div>
<a class="anchor" id="a6d1daf7ab6f2ba83f57ff67ae6f571fe"></a>
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          <td class="memname">uint32_t NVIC_Type::RSERVED1[24]</td>
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<p>Reserved. </p>

</div>
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<p>Offset: 0xE00 ( /W) Software Trigger Interrupt Register. </p>

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